A. Field of the Invention
The present invention relates to electronics packaging of a circuit or one or more components, and in particular, to electronics packaging of plural solid state components on an electrically conductive lead frame or substrate in a single package.
B. State of the Art
A widely used method for manufacturing surface mount or through-pin (socket mount) electronic devices or circuits is to assemble one or more solid state components on a lead frame and then encapsulate the component(s) in a package. This is sometimes referred to in the industry as electronics packaging.
The lead frame is essentially the “skeleton” or framework of the plastic-encapsulated package, providing mechanical support to the solid state component(s) or circuit during its assembly into a finished product. The solid state component typically is a die, sometimes called a chip or a bare chip. The lead frame includes a die paddle to which one or more die is/are attached or mounted and leads which serve as the means for external electrical connection. The die is electrically connected to the leads or terminals by wires or other conductors (e.g. through wire bonding, or tab or clip bonding, or with electrically-conductive bars on a bridge frame).
Plastic package type lead frames are many times made of alloys that meet the following critical properties: good adherence to the molding compound, a coefficient of thermal expansion as close as possible to those of the die and the molding compound, high strength, good formability, and high electrical and thermal conductivities. A copper alloy is one type of material. Multiple lead frames can be mass-produced in an automated fashion in a single flat sheet of metal (e.g. by stamping or etching). After the shape of each lead frame in the sheet is created, they can be singulated into strips of plural lead frames or into individual lead frames. One or more die (e.g. solid state devices) are mounted on each lead frame. This can also be automated. Final assembly includes any needed electrical connections between die and leads, and encapsulation with a plastic material to create a “package” with exposed electrical leads. Automated processes also exist for these conventional steps.
In the specific example of a power factor correction (PFC), continuous conduction mode (CCM) rectifier electronics package for high voltage applications, it is desirable to have fast switching speed, low power dissipation, and high voltage capability. One solution is to use two low voltage diodes in series in one package. As will be discussed below, this can require the addition of a ceramic isolation layer into an existing package and series connection of the two chips internally. However, the ceramic board is expensive and the manufacturing and assembly process is complex. An alternative solution is to use a single SiC or GaAs diode, which has good electrical characteristics. However, such a device needs an even more complicated manufacturing process and has a higher (e.g. three to five times) cost and investment than the tandem series-connected low voltage PFC diodes mentioned previously. Therefore, there is room for improvement in the state of the art.
FIGS. 1A-C illustrate one state of the art configuration for connecting two low voltage semi-conductor diodes in series in one lead frame package for a high voltage power rectifier. Package 10 includes a lead frame 30 with a die mounting surface 31 on the die paddle, an integrally connected and outwardly extending lead or support 34, and two electrically isolated leads 36 and 38. All parts of lead frame 30 are made of highly electrically conductive material.
To connect die 16 and 18 in series between leads 36 and 38, an isolation board 20, usually made of ceramic, is fixed (e.g. adhered) to mounting surface 31 of the die paddle of lead frame 30. Conduction pads (e.g. of copper) 12 and 14 are fixed (e.g. adhered) to the top surface of isolation board 20 at spaced apart positions. Sometimes one of copper pads 16 or 18 stands out as one lead. The ceramic isolation board requires good heat conduction capability. Die 16 and 18 are attached on copper pads 12 and 14 respectively by a solder joint. Finally, wires 22, 24, and 26 are connected by wire bonding techniques to serially electrically connect leads 36 and 38 to chips 16 and 18 as shown in FIGS. 1A-C. Both die 16 and 18 are P-side up. Mounting surface 31 of die paddle lead frame 30 is essentially flat. Wire bonding is a well-known method of electrical connection of die to lead in microelectronic or semiconductor device fabrication and automated assembly processes.
As indicated in FIGS. 1A-C, each of the semiconductor diodes has a “P” side, region, or block with exposed P-type material (P doped silicon or other semiconductor material), and an “N” side, region or block with exposed N-type semiconductor material (N doped silicon or semiconductor material). Conventionally, each is mounted “P side up” on lead frame die mounting surface 31. For series connection of the two diodes and a lead for each diode, a wire or other conductor must be electrically connected between a first lead and the P side of a first diode and between second lead and the N side of a second diode. Another wire or conductor must be electrically connected between the N diode of the first diode and the P side of the second diode. As diagrammatically illustrated in FIG. 1B, an electrical current path between P and N sides of each diode 16 and 18 (see broken lines 23 and 27 in FIG. 1B) completes the series connection. Through-hole 54 is typically used to connect the lead frame of the package to a heat sink.
FIG. 2A illustrates an exemplary method of manufacturing steps for package 10 of FIGS. 1A-C. As can be seen, this state of the art assembly process requires the addition of several pieces to the lead frame prior to mounting of the die. Specifically, it requires the mounting of ceramic isolation board 20 and copper pads 12 and 14. Also, three wire bonding connections are used; one between lead 38 and copper pad 14 (which essentially is the “N” side of die 18), one between the top or “P” side of die 18 and copper pad 12 (essentially the “N” side of die 16), and one between the top or “P” side of die 16 and lead 36. This results in the series connection shown in schematic form in FIG. 2B. The foregoing package includes multiple parts and steps to create the series-connection tandem diode circuit. Although simpler and cheaper than using one SiC or GaAs diode, this tandem diode assembly process is also relatively complex. The above-described factors increase cost and resources needed to manufacture such circuits and packages. It can be further appreciated, such multiple parts, including isolation board 20, can make it more difficult to maximize performance of the rectifier device (e.g. switching speed and power dissipation). They also can increase the size of the device, which is contrary to desirability to improve density of circuits and decrease package size of devices.
Therefore, a need has been identified to improve over or solve problems and deficiencies in the state of the art. For example, it can be beneficial to reduce the cost of materials, manufacturing, and assembly of such devices and the circuits in which they are used, while at the same time achieving better electrical and physical characteristics for such devices (e.g. thermal transfer, switching performance, size, and power dissipation) and for the circuits in which they are use (e.g. power density).
The housing or packaging which chips typically come in for plugging into (socket mount) or soldering onto (surface mount) a printed circuit board are to protect the packaged chip or chips. But it is not a trivial matter because the electrical characteristics of the electronics must be maintained. Electronics packaging is a large and complicated industry. It is further complicated by continued pressure to provide more and more I/O interconnections to a die (bare chip) that increasingly are shrinking in size. Smaller package sizes are also desirable for miniaturization of, for example, many electronic devices, including the fast expanding number of handheld devices. But at the same time, it is desirable to minimize manufacturing costs and complexity. Thus, there are a variety of sometimes conflicting factors involved in electronics packaging.